My spislave model in Opencores website

spislave is a minimalist spislave IP core that provides the basic framework for the implementation of custom spio devices. The core provides a means to write up to 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface. A full Icarus Verilog test bench is available. Test it for yourself, using the free Icarus Verilog simulator and the free GTKWave wave form viewer.

http://www.opencores.org/project,spislave

Other projects i am working on are :

http://www.opencores.org/project,spigpio
http://www.opencores.org/project,i2cgpio
http://www.opencores.org/project,i2clcd